Speed-Independent PRs Simplified Timed PRs

In this paper we present a synthesis method that utilizes timing constraints to generate timed asynchronous circuits. By unfolding the cyclic graph specification of an asynchronous circuit into an infinite acyclic graph, we are able to use efficient algorithms to analyze the given timing constraints. We derive a sufficient condition for the removal of redundancy in the specification. Based on this condition, we only need to analyze a finite subgraph of the infinite acyclic graph for derivation of a correct implementation. To the reduced specification, we apply a systematic synthesis procedure that further optimizes the implementation based on the timing constraints. Using realistic circuit examples, we demonstrate that the resulting timed implementation can be significantly reduced in complexity from its speed-independent counterpart while remaining hazard-free under the given timing constraints.